Research & Development Efforts

During 2008, UMC focused on improving transistor performance and yield on 45/40nm process technology, which has already entered production. The 45/40nm node simultaneously introduces new materials and process modules. It incorporates sophisticated immersion lithography for its critical layers and the latest transistor advancement such as ultra shallow junction and mobility enhancement techniques that include embedded SiGe source/drain processes, dual stress liners, and ultra low-k dielectrics. Its product applications include mobile baseband, application processor, wireless network, and portable consumer electronic products. In 2009, R&D effort will focus on new product debugging and yield improvement, as our customers launch their next generation 40nm products.

UMC has also produced the foundry industry's first fully functional 28nm SRAM chips. This independently developed UMC technology features very small six-transistor SRAM cell sizes of approximately 0.122 um² to provide almost twice the density of 40nm technology. UMC utilized advanced double-patterning immersion lithography and strained silicon technology to produce the chips.

To address the fast-changing semiconductor technology challenges of the future, UMC will strengthen its independent R&D for advanced foundry technologies through cooperative partnerships with suppliers, universities, and research institutes around the world by joining SEMATECH. The relationship will focus on research and development for exploratory technologies on 300mm wafers, including 22nm and beyond process generations.

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SoC Enabling Technologies

SoC designers today require proven design support solutions to help them overcome the challenges encountered during the design cycle. UMC has successfully introduced a Reference Design Flow with silicon-proven design methodologies down to 65-nanometer technologies. The UMC Reference Design Flows incorporate 3rd-party EDA vendors' baseline design flows to address issues such as timing closure, signal integrity, leakage power and Design For Manufacturability (DFM). The flow has been successfully validated utilizing the open-source LEON2 SPARC processor in 65-nanometer silicon. They cover schematic/RTL coding all the way to GDS-II generation and support Cadence, Magma, Mentor and Synopsys EDA tools. The availability of UMC's newest and most comprehensive reference flows help SoC designers find the easiest path to silicon success for advanced technologies. In order to address customer's SoC design needs of intellectual properties (IP), UMC operates an extensive coverage of 3rd-party IP partnerships with industry-leading vendors including ARM, Virage, Synopsys, Faraday, and Silicon Image, offering a range of services from physical libraries to analog mixed-signal IP that supports industry standards such as PCI-E, SATA, and HDMI. In addition, UMC successfully developed a series of reliable, high quality intellectual properties (IP). These include DFM-compliant, process-tuned 65-nanometer libraries, ultra high-speed PLL, and various state-of-the-art analog mixed-signal IPs that support industry standards for advanced audio/video applications, all of which will be utilized in customer SoC designs to help shorten their design cycle time.

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Fundamental Research

For exploratory technologies, the true limits of immersion lithography are being constantly challenged, while further Resolution Enhancement Techniques (RETs) are being explored actively. With regard to 28nm, several customers are involved in the current 28nm development stage, with progress going smoothly at UMC's R&D center in Tainan, Taiwan. This 28nm process is expected to enter pilot production in the second half of 2010. For this technology node, UMC will provide low power and high performance Poly/SiON and HK/MG process technologies to meet the performance and power needs of various applications. UMC will also provide foundry services for customized 32nm technologies based on its 28nm process platform.

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