0.13 微米設計單元資料庫

透過提供眾多廠商的綜合免費設計單元資料庫，聯電重新改革了晶圓專工產業。
除此之外，聯電同時還提供其他的收費設計單元資料庫。

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免費設計單元資料庫

Virtual Silicon 0.13um Library - High Speed (FSG) Process
Standard Cell 552 high density standard cells 9-track cell architecture, performance optimized for 300~800 MHZ Average cell density of 220K gates/sq.mm Multiple drive strengths Layout using metal 1 only Scan version of every flip-flop available Fully contacted well ties Accurate modeling and characterization for timing and power Open architecture developers kit available	Inline and Staggered I/O 400+ 3.3V I/O pads Pad pitch: 70um (in-line), 35um (staggered) Multiple current drives up to 16mA Input buffer types - Pull-up/pull-down resistor, pad keeper, normal/Schmitt Output and bi-directional buffer types with slew rate control Silicon proven ESD and latch-up structures Analog power pads, crystal pads Open architecture developers kit available

PLL Compiler	Single Port SRAM, Dual Port SRAM and Diffusion ROM Compilers
Programmable input, output frequencies and duty cycle Input frequency range: 20 MHz - 200 MHz Output frequency range: 50MHz - 1GHz PLL module entirely located in the I/O pad rings Dedicated analog power supply pins Build-in ESD and latch-up protection structures	Synchronous reads/writes Static design with zero standby current Byte write capability Routable over the core with higher metal layer Ability to compile to multiple aspect ratio Scan and BIST support

Faraday 0.13um Library - Low Leakage (FSG) Process
Standard Cell and I/O: Power supply (internal logic and I/O): 1.2V Second power supply (I/O): 3.3V 8-track cell architecture; Cell high = 3.2um. X grid = 0.4um, Y grid = 0.4um. Gate delay = 33ps/stage @ 1.2V, F.O. = 1 Low power: 0.006uW/Gate/MHz @ 1.2V, 2-Input NAND, F.O. = 2 Ultra high density: 250K Gates/mm2 @Utilization = 100% (i.e. 1million transistors / mm2)	Fat/Slim profile I/O optimized for Core/Pad limited design Programmable input characteristics for pull up/down/ keeper and Schmitt trigger Programmable output driving current 2-8mA by steps of 2mA, 4-16mA by steps of 4mA. Programmable output slew rate control Mixed 1.2V/3.3V interface Wide selection of I/O buffers: 3.3V, 3.3V with 5V tolerant.

Single Port SRAM, Dual Port SRAM, One Port Register File, Two Port Register File, and Via2 ROM Memory Compilers
	Synchronous reads/writes		Ability to compile to multiple aspect ratio
	Static design with zero standby current		Scan and BIST support
	Byte write capability		Power port connection support
	Provides both high speed and low power SRAMs		Zero hold time for inputs

Faraday 0.13um Library - High Speed (FSG) Process

Standard Cell and I/O: Power supply (internal logic and I/O): 1.2V Second power supply (I/O): 3.3V 8-track cell architecture; Cell high = 3.2um. X grid = 0.4um, Y grid = 0.4um. Gate delay = 17ps/stage @ 1.2V, F.O. = 1 Low power: 0.006uW/Gate/MHz @ 1.2V, 2-Input NAND, F.O. = 2 Ultra high density: 250K Gates/mm2 @Utilization = 100% (i.e. 1million transistors / mm2) Fat/Slim profile I/O optimized for Core/Pad limited design Programmable input characteristics for pull up/down/ keeper and Schmitt trigger Programmable output driving current 2-8mA by steps of 2mA, 4-16mA by steps of 4mA. Programmable output slew rate control

Mixed 1.2V/3.3V interface Wide selection of I/O buffers: 3.3V, 3.3V with 5V tolerant. Single Port SRAM, Dual Port SRAM, One Port Register File, Two Port Register File, and Via2 ROM Compilers Synchronous reads/writes Static design with zero standby current Byte write capability Provides both high speed and low power SRAMs Ability to compile to multiple aspect ratio Scan and BIST support Power port connection support Zero hold time for inputs

收費設計單元資料庫

Virage Logic 0.13um Memory Compiler

Virtual Silicon 0.13um Library - Low Leakage Process
Standard Cell 522 high density standard cells 9-track cell architecture Average cell density of 200K gates/sq.mm Multiple drive strengths Layout using metal 1 only Scan version of every flip-flop available Fully contacted well ties Accurate modeling and characterization for timing and power Open architecture developers kit available	Inline and Staggered I/O 400+ 3.3V I/O pads Pad pitch: 70um (in-line), 35um (staggered) Multiple current drives up to 16mA Input buffer types - Pull-up/pull-down resistor, pad keeper, normal/Schmitt Output and bi-directional buffer types with slew rate control Silicon proven ESD and latch-up structures Analog power pads, crystal pads Open architecture developers kit available

PLL Compiler	Single Port SRAM, Dual Port SRAM, Two Port Register File, and Diffusion ROM Compilers
Programmable input, output frequencies and duty cycle Input frequency range: 24 MHz - 200 MHz Output frequency range: 50MHz - 1GHz PLL module entirely located in the I/O pad rings Dedicated analog power supply pins Build-in ESD and latch-up protection structures	Synchronous reads/writes Static design with zero standby current Byte write capability Routable over the core with higher metal layer Ability to compile to multiple aspect ratio Scan and BIST support

Dolphin Technology 0.13um Library
Standard Cells		Special Purpose I/Os Staggered pad design with 30u pitch Core/Area I/O pads for flip chip (C4) 200um & 225um LVDS drivers and receivers LVPECL PCI-X for 133 MHz operation backwards compatible with PCI-66/33 MHz PVT compensated, Impedance Matched, Source Series Terminated 1.5V IO (SDR/DDR) PVT compensated, Impedance Matched, Source Series Terminated 1.8V IO (SDR/DDR) PVT compensated, Impedance Matched, Source Series Terminated 2.5V IO (SDR/DDR) PVT compensated, Impedance Matched, Source Series Terminated 3.3V IO (SDR/DDR) SSTL2 (DDR) Class I/II HSTL Class I/II SPI-4.2 SigmaRAM 322-MHz (DDR) DDR I / II & HSTL pad in one HyperTransportTM (LDT) RX/TX/IO macros for licensed AMD K8 bus partners @1.6Gbs PCI-66/33 GTL, GTL+, AGTLP AGP 2X/4X/8X USB 1.1/2.0 GMII, RGMII
	Full custom standard cell library consisting of about 500 cells
	Single metal layer design for high routing utilization
	10-track layout
	High speed and high density
	Accurate timing and power models
	Complete models and views for synthesis and functional simulation tools
Standard I/Os
	Staggered pad design with 30um pitch
	Core/Area I/O pads for flip chip (C4) 200um & 225um
	LVCMOS, LVTTL & Schmitt Trigger input
	I/O Drive strengths 2/4/6/8/10/12 mA 1.2V core with 3.3V output
	I/O Drive strengths 2/4/6/8/10/12 mA 1.2V core with 3.3V output /5.0V tolerance
	I/O Drive strengths 2/4/6/8/10/12 mA 1.2V core with 2.5V output
	I/O Drive strengths 2/4/6/8/10/12 mA 1.2V core with 2.5V output /3.3V tolerance
	Pull-up, pull-down, sustain level options
	4 different slew rate keeper options, JTAG inputs for testability, Schmitt trigger inputs
	Level shifts from 1.2V core up to 3.3V I/O supply and from 3.3V to 1.2V

Memory Compilers with and without Redundancy
	Single port SRAM, Dual port SRAM, 2-Port Register File and 4-Port Register File compilers using RAMpiler TM development system and user interface		- Multiple output drive strengths   - Different power ring design configurations   - Bit Write Mask or Word (global write) options   - Write through, transparent write   - BIST Mux option on the inputs   - Row redundancy   - Column/IO redundancy 2-Port (1R/1W) register file compiler 4-Port (2R/2W) register file compiler       Specialty Memories Binary BCAM memories and CAM compilers using CAMpilerTM technology Ternary TCAM memories and CAM compilers using CAMpilerTM technology Custom single instance large density SRAMS with redundancy up to 24 Mbits Custom Register Files with different configurations such as: 1W/4R, 3W/3R, 1W/8R, 2W/4R, 3W/5R, etc.
	RAMpiler + TM with row and column redundancy of up to 2 rows & 2 columns/IOs
	-	Synchronous reads/writes
	-	Static design with zero standby current
	-	Ability to compile to multiple aspect ratios
	-	Up to 1.1Mbit single instance
	-	Up to 288 bit word
	-	Up to 16K words deep
	-	Fully routable over the memory with higher metal layers
	-	Small set-up and zero hold times
	-	Power ring size based on frequency of operation and load
	-	Multiple pin placement and layer options
	-	Multiple power ring metal layer and configuration options
	-	Register output options

Artisan 0.13um Library
Standard Cells		In-line and staggered I/O
	1000+ high performance standard cells		3.3V
	9-track cell architecture high speed		Pad pitch: 70um (In-line), 35um (Staggered)
	Average cell density of 156K gates/sq.mm		Multiple current drives up to 16mA
	8-track cell architecture high density		Pull ups, Pull downs, switchable
	Average cell density of 192K gates/sq.mm		Hysteresis
	Multiple drive strengths		Built-in level shifting
	Silicon proven
	Scan version of every flip-flop available
	Compatible with mixed signal environment
	Compatible with mixed signal environment