0.15 微米設計單元資料庫

透過提供眾多廠商的綜合免費設計單元資料庫，聯電重新改革了晶圓專工產業。 除此之外，聯電同時還提供其他的收費設計單元資料庫。

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免費設計單元資料庫

Virtual Silicon 0.15um ASIC Library
Standard Cell 500+ high density standard cells 8-track cell architecture, performance optimized for 300~800 MHZ Average cell density of 150K gates/sq.mm Multiple drive strengths Layout using metal 1 only Scan version of every flip-flop available Fully contacted well ties Accurate modeling and characterization for timing and power Open architecture developers kit available	Inline and Staggered I/O 700+ 3.3V &3.3V/5VT I/O pads Pad pitch: 60um (in-line), 40um (staggered) Multiple current drives up to 24mA Input buffer types – Pull-up/pull-down resistor, pad keeper, normal/Schmitt Output and bi-directional buffer types with slew rate control Silicon proven ESD and latch-up structures Analog power pads, crystal pads Open architecture developers kit available

PLL Compiler	Single Port SRAM, Dual Port SRAM, Two Port Register File, and Diffusion ROM Compilers
Programmable input, output frequencies and duty cycle Input frequency range: 20 MHz - 200 MHz Output frequency range: 50MHz - 1GHz PLL module entirely located in the I/O pad rings Dedicated analog power supply pins Build-in ESD and latch-up protection structures	Synchronous reads/writes Static design with zero standby current Byte write capability Routable over the core with higher metal layer Ability to compile to multiple aspect ratio Scan and BIST support