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0.25
微米設計單元資料庫
透過提供眾多廠商的綜合免費設計單元資料庫，聯電重新改革了晶圓專工產業。
除此之外，聯電同時還提供其他的收費設計單元資料庫。
免費設計單元資料庫
| Artisan
0.25um Library |
| Standard Cell |
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437+ high density standard
cells |
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8-track cell architecture |
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Average cell density of
64K gates/sq.mm |
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Multiple drive strengths |
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Routable in 3, 4, or 5
metal layers |
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Comprehensive design tool
support |
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Process specific electrical
and physical tuning |
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| Single
Port SRAM and Dual Port Memory Compilers |
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Exceptional speed |
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Broadly configurable |
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Low active power and leakage-only
standby current |
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Complete set of tool models
and characterization data |
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Flexible power
routing |
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Zero hold time (data,
address and control inputs) |
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Architecture
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Word
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Bit
|
Mux
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Size
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Access Time (ns)
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Single Port Sync. SRAM
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16 - 8K
(Increment: 2X mux)
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2 - 128
(Increment: 1)
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4, 8,
16
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32 bit - 512 Kbit
|
4K x 16
Typical: 1.55
Worst: 2.43
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Dual Port Sync. SRAM
|
16 - 8K
(Increment: 2X mux)
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2 - 128
(Increment: 1)
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4, 8,
16
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32 bit - 512 Kbit
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4K x 16
Typical: 1.68
Worst: 2.83
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收費設計單元資料庫
| Faraday
0.25um Library |
| Standard Cells |
|
400+ high performance
standard cells |
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8-track cell architecture |
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Average cell density >60K
gates/sq.mm |
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Optimized multiple drive
strengths |
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High porosity and routability |
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Scan version of every
flip-flop available |
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Ultra low power cell available |
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Gated input for preventing
leakage |
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Fully tool models support |
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| Inline and Staggered
I/O |
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2.5V, 3.3V I/O pads |
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2.5V/3.3VT, 3.3V/5VT I/O
pads |
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Support over 500+ IO Functions |
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Pad pitch: 65um (In-line),
40um (Stagger) |
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Programmable current drives
and slew rate control from 2mA to 16mA |
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Programmable pull-up/pull-down
resistor, normal/ Schmitt trigger |
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Provide 90+ programming
features in one I/O pad |
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In-line to staggered I/O
corner available |
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| Analog |
Single Port SRAM, Two Port SRAM, Diffusion
and Via2 ROM Compilers |
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Excellent high PSRR and
low jitter Phase-Locked Loops |
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10-Bit DAC 200MHz |
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8-Bit ADC 135MHz |
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Power-on-reset circuit |
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Low VDD Detector |
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RC oscillators |
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Voltage Regulators |
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Comparators |
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Crystal pads |
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Synchronous reads/writes |
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Static design with zero
standby current |
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Byte write capability |
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Provides both high speed
and low power SRAMs |
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Ability to compile to
multiple aspect ratio |
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Scan and BIST support |
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Power port connections
support |
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Zero hold time for inputs |
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Architecture
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Word
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Bit
|
Mux
|
Size
|
Access Time (ns)
|
|
Single Port Sync. SRAM
|
4 - 64K
(Increment:2X mux)
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1 - 128 (Increment: 1)
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1, 2, 4, 8, 16
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4 bit - 512 Kbit
|
4K x 16
Typical: 1.9
Worst: 3.1
|
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Two Port Sync. SRAM
|
4 - 16K
(Increment:2X mux)
|
1 - 80
(Increment: 1)
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1, 2,
4, 8,
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4 bit - 160 Kbit
|
4K x 16
Typical: 2.1
Worst: 3.3
|
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Via2 ROM
|
128 - 64K (Increment:128X mux)
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2 - 128 (Increment: 1)
|
1, 2,
4, 8,
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256 bit - 1 Mbit
|
4K x 16
Typical: 3.3
Worst: 5.5
|
|
Diffusion ROM
|
128 - 64K (Increment:128X mux)
|
2 - 128 (Increment: 1)
|
1, 2,
4, 8,
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256 bit - 1 Mbit
|
4K x 16
Typical: 7.3
Worst: 12.1
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| Standard Cells |
Memories |
|
1000+ cells |
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Single port register
files, 24Kbits |
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10-track cell architecture |
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Two port register files, 24Kbits |
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Average cell density of 36K
gates/sq.mm |
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Multiple drive strengths |
Analog |
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Silicon proven |
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800MHz Phase Locked Loop (PLL) |
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Scan version of every flip-flop
available |
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266MHz Video Phase Locked Loop
(PLL) |
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Compatible with mixed signal
environment |
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Fast Crystal Oscillator 4-33
MHz |
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Accurate timing and power models |
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| In-line and Staggered I/O |
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3.3V/5VT |
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Pad pitch: 76.8mm (In-line),
52.8mm (Staggered) |
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Multiple current drives up to
16mA |
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Pull ups, Pull downs, switchable |
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Hysteresis |
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Built-in level shifting |
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