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General
Questions
1.
Why is GDSII the preferred tape-out database format in UMC?
The customer's database must go through DRC sign-off procedure before
taping out for pilot run or production. We reviewed this procedure
and found that the cycle time was very inconsistent due to the various
formats of the database. To shorten the cycle time and improve the
productivity and the efficiency, we would like to ask customers
for their cooperation in unifying the format of their tape out database.
Currently, three different formats are used for tape-outs. They
are GDSII, MEBES, and CFLT. Thus, we do not support tapeouts in
CIF or other formats. Please see Table 1 below for the differences
in their characteristics.
| Table 1. Characteristics
of different database formats |
| |
Feature |
Hierarchy |
File Size |
| GDSII |
Standard transportation format |
Keep |
Small |
| MEBES |
Mask house format |
Flatten |
Large |
| CFLT |
CATS (EDA tools) format |
Flatten |
Large |
Table1 Characteristics of different database
format
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2.
Does UMC have a preferred layer-mapping table (layer name vs. layer
number) for customers to follow in their GDSII database? If so,
how does it look like?
UMC provides an official layer-mapping table for customers to facilitate
GDSII data transferring. UMC strongly recommends customer to use
the official layer mapping in a GDSII database taped out to UMC.
It will save DRC sign off time and make the result correctly.
The layer-mapping table is a formal document (GT-RPT-000601-001),
which can be applied from UMC Technology Information Center (TIC).
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3.
Which command files (DRC/LVS/LPE) and their corresponding EDA tools
are supported by UMC?
UMC's Design Support Division (DS), provides DRC, LVS and LPE command
files for both logic and mixed-mode processes in all technologies.
They can be downloaded from UMC's website (www.umc.com).
Please check the web for command file availability.
UMC also cooperates with all mainstream EDA tool vendors (Cadence,
Mentor and Synopsys) in allocating resource and finding out possible
solutions for UMC's customers.
| Design Verification
Tool Support List |
| |
Cadence
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Mentor
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Synopsys
|
Sequence
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Magma
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Spring Soft
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DRC
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Assura
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Calibre
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Hercules
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* Dracula
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LVS
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Assura
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Calibre
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Hercules
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* Dracula
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LPE
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Assura RCX
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XRC (xCalibre)
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Arcadia
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Columbus
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Blast Fusion
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* Dracula
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Star RCXT
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Fire&Ice (QX)
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HyperExtract
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TF
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Laker
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| * Dracula only supports 0.18um
process and above. |
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4.
What can a customer do if the customer can not find the command
file on UMC Web site that customer wants ?
For those command files that are not listed, the customer can request
them through their UMC Customer Engineer (CE).
The CE will evaluate and then forward the request to the Design
Support Division (DS) . DS will arrange resource to support it and
reply the possible release date for the CE to inform the customer
as reference.
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5. What should be done
before a customer uses a UMC command file?
| To prevent problems during the
DRC/LVS/LPE execution, the customer should verify the following
items: |
| 1. |
Examine the consistency of
the command file and the design rule by inspecting the specification
name and the version number. |
| 2. |
Read the header of a command
file carefully. Important information (listed below) can be
found in the header section. For example: |
| |
a. General information including
spec name, version, originator, adaptive version of EDA tools,
etc. |
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b.1 Specific rules which are
not implemented in the DRC command file. |
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b.2 The device table that lists
all available device definitions in the LVS command file. |
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c. Direction of command file usage. For example, option setting
to include or exclude a set of special checks, generating
methodology of an input layer (N+implant could be a drawn
layer or a derived layer generated by tooling).
|
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6.
What is UMC's recommended grid size for customer layout and verification?
Please refer to the definition in related TLR or global rule.
If there is no definition in TLR or global rule :
For 0.15um and above technology, UMC recommends 0.01um as customer's
layout grid. UMC will use 0.001um as verification grid in order
to check customer's database to gain better precision. For 0.13um
and 90nm technology, it's mandatory for UMC's customer to set layout
grid in units of 0.005um. (0.005um, 0.01um, etc.)
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7.
Are there any LVS to LPE flows that UMC recommend ?
For the neutral standpoint, UMC does not recommended any flow for
customer. Customers could decide their own flow by consider what
tools they have.
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8.
How long does a customer need to wait for a new created LVS or LPE
file from UMC?
For a normal LVS & LPE (new created) case is about 2 ~ 3 weeks,
if related DRM is available.
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DRC Questions
1.
What is the DRC Sign-off flow in UMC?
The purpose of DRC (Design Rule Check) sign-off is to verify customer's
layout to meet UMC's design rules. Some customers adopt different
libraries or embed customized blocks in their designs. In order
to make sure the layout of a customer's design is acceptable by
UMC's layout rules, UMC has come up with a DRC Sign-off flow. It
was developed by DS/engineers, BG/customer engineers and Fab/PEI
engineers.
When a DRC violation is found in the sign-off procedure, it will
be either passed to the customer through his UMC CE or reviewed
by Fab PEI engineers. The DRC sign-off is an important procedure
for foundry service to improve production yield and avoid potential
problems caused by possible layout rule violations.
Design Rule Check Sign-Off Flow
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2.
How does UMC guarantee to use a correct database for DRC sign-off?
Why is file size a must-be item in DRC sign off?
UMC uses gds file name, date of file, top cell name and file size
to identify the customer database and a file ID is assigned to each
database. So file size is a key item to check the correctness of
the database in case of any data losses during file transferring.
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3.
Are there any "metal coverage rule" requirements for a
customer's tape-out in UMC?
Yes, there is a metal coverage rule check that must be satisfied.
The requirement varies according to process. Metal coverage check
is included in UMC DRC command files. Service of transparency checks
of masks and dummy metal placement are provided by the UMC Mask
Engineering Support Division (MES) and the mask house.
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4.
Why is the "antenna rule check" not included in the generic
DRC command file for Dracula in UMC?
UMC does not include
the "antenna rule check" in the DRACULA command file because
it cannot recognize the geometry of diodes connecting to the net
of antenna concern. UMC would like to prevent the customer from
running into trouble due to Dracula's limitations when building
up the connection information. Cadence has issued an internal PCR
(No. 482163) to fix this problem. Antenna check is not supported
by Diva because Diva is a tool for cell-level/macro-level verification.
What happens if a customer needs the antenna
rule check?
Ans.UMC antenna check is supported by Calibre/Mentor Graphics, Hercules/Synopsys
and has implemented into DRC command files respectively. UMC also
provides trial-run service by Calibre.
Note: Antenna rule check on Calibre and Hercules does not have this
problem.
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5.
Does UMC provide any efficient checking methodology of DRC for logic
design with embedded memory ?
Layer-marking is one
of the approaches to execute the whole chip DRC on an embedded memory
cell in a design. It requires a very careful work on the boundary
conditions for mask marking and is commonly used by vendors.
UMC prefers using memory marker-layers
where memory mark layers are well-defined in UMC embedded memory
database. In DRC files, 2 sets of the rule checks are applied to
logic portion and cell portion respectively and differentiated by
the mark layers. With memory marker layers, the violations at memory
area are eliminated so that the violations at other area can be
reviewed completely.
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6.
Can OPC block layers be used as memory marker layers?
It's not recommended due to boundary violations
although their shapes are similar to memory marker layers'. Some
memory compilers that are out-of-date can't generate memory marker
layers. For those memory cells without memory marker layers, it
can reduce the violations and expedite the DRC review by using OPC
layers as memory marker layers.
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7.
How does UMC maintain, update and validate its DRC command files?
| 1. |
UMC keeps the version of DRC
command files match the parent documents. The internal DRC QA
flow is shown at the next page. |
| 2. |
DRC QA patterns are updated
right after the TLR is revised and applied to validating DRC
command files. |
| 3. |
UMC libraries and SRAM cells
are also applied. DRC QA patterns, UMC libraries and SRAM cells
are noted as QA database in the DRC QA flow. |
| 4. |
The programming engineers are
asked to update DRC command files once a bug is found in DRC
sign-off. The QA patterns are also updated for the new corner
case. |
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8.
What is the position of UMC on supporting Assura, Vampire and Diva
from Cadence?
| 1. |
UMC supports Assura
for 0.35um and below technology. |
| 2. |
Vampire is not supported. |
| 3. |
Diva is not supported. |
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9.
How to define the term ?"metal line end" in TLR?
UMC uses following interpretation
for Metal overlap Via rule:
Acceptant criterion of "Metal enclosure (of Via) in line-end
direction by 0.1um"
is defined as -
1. Metal overlap Via by 0.1um in x-direction (+x and -x) OR
2. Metal overlap Via by 0.1um in y-direction (+y and -y).
In other words, the direction where Metal
extends in both opposite sides of
Via is treated as the direction of the line.
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10.
How to define the area of fuse, pad, ESD, dummy and slot?
Marker layers are applied to the identification
of fuse, pad, esd, dummy and slot. Without marker layers, the specific
DRC rules such as fuse DRC rule will not be applied to the target
area and will check nothing. For the marker layer names and corresponding
gds layer numbers, please refer to TLR, global rule and UMC official
layer mapping file.
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11.
Does UMC provide any dummy via insertion scripts?
Yes, dummy via insertion scripts can be provided
for 0.15um and below. If customers need this service, please contact
the account manager.
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LPE
Questions
1.
Where can the process parameters for RC extraction tools be found?
Process parameters for RC extraction can be found on UMC's website.
Simply login into the TDS account and go to Design Rule/Document
Type Category. Parameters (e.g. ILD, IMD, thickness, dielectrics,
min width and min spacing for each layer) can be found at categories:
"Electrical Design Rule", "Interconnect Capacitance
Model" and "Topological Layout Rule".
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2.
What kinds of LPE command/rule files (vs. vendors) are commonly
provided by UMC?
The support lists of LPE tools are shown as the following table.
Nautilus is not supported due to lack of vendor's support. Dracula
and Star-RC are not recommended due to accuracy concern. However,
UMC still support Dracula and Star-RC.
| Company |
Tool Name |
Synopsys
|
Star-RC; StarRC-XT; Arcadia |
| Cadence |
DraculaLPE; HyperExtract; Assura;
Fire and Ice |
| Mentor Graphics |
xCalibre / XRC |
| Sequence |
Columbus |
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3.
How to modify the command file to get MOS parameters, including
AD, AS, PD, and PS by using Dracula's LPE tool?
Add the following commands under the description and operation blocks
of the file will have Dracula take the MOS parameters.
| |
*description
PARSET ICHI AREA PERI
*operation
ELEMENT MOS[N] NGATE POLY NSD PWELL
ELEMENT MOS[P] PGATE POLY PSD NSUB
LEXTRACT ICHI PSD BY NODE PDIFF
LEXTRACT ICHI NSD BY NODE NDIFF
ATTACH MOS[P] PDIFF
ATTACH MOS[N] NDIFF. |
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4.
How are the areas and perimeters of the source and drain being calculated?
Is Dracula's junction capacitance extraction methodology consistent
with ACM=3 defined in UMC's HSPICE model?
The above figure shows two transistors in
series, and they share the same diffusion for the source and drain.
With Dracula, a "NRX-EXTRACT" command can extract resistance
values of both source and drain of the MOS. The MOS parameters in
the output SPICE net_list will include L, W, AD, PD, AS, PS, NRS,
and NRD. The internal calculation function is described in Chapter
11 of the Dracula Reference. Users could also define their own PARSET
to extract the area and perimeter of MOS source/drain with their own
equations.
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5.
How does a customer add the capacitance of the gate-oxide by using
DRACULA LPE?
First, find the values of Ca and
Cf in the spec document "Electrical Design Rule", then
add the following commands with both values on <Carea> and
<Cperimeter> respectively under the operation block:
| |
PARASITIC CAP[XX] NGATE POLY
NDIFF
PARAMETER <Carea> <Cperimeter>
PARASITIC CAP[XX] PGATE POLY PDIFF
PARAMETER <Carea> <Cperimeter> |
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6.
How does UMC simulate conformal dielectric structure with HyperExtract
LPE?
Since HyperExtract supports planar dielectric structure only, UMC
uses planar approach to implement conformal dielectric structure.
The errors of planar approach are less than 5%.
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7.
What is WEE?
WEE stands for Wire Edge Enlargement. Any effect (from manufacturing
behaviors) that causes the real dimension not equal to the drawing
is known as WEE. Bias, Dishing, Erosion, trapezoid shape are included.
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8.
Does UMC support WEE on LPE files?
Currently, only few RC extraction tools support WEE effect. Some
LPE files on UMC website include the WEE factor. Please read the
header of command file for reference. You can contact UMC for information
in detail.
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9.
What is the difference between Cell level extraction and Transistor
level extraction?
CCell level extraction will only extract the routing layers exclude
the cells, Transistor level extraction will extract parasitic RC
down to the device level. If customers put the standard cells in
the layout and already know the value of the cells, they could use
the Cell level extraction flow.
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10.
How does RC extraction tool treat the parasitic L?
Currently only few tools claim they can do the L extraction (called
RLC extraction tool), and most of the RC extraction tool vendors
set the L extraction as their milestone.
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11.
What is the LPE QA flow in UMC?
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12.
What kind of action will be taken in UMC if there are noticeable
differences between silicon data and RC extraction result?
We will try to find out the possible causes of differences: the
measurement error, process file typo, RC extraction tool accuracy
issues or if the process documents is out of date. Once the cause
is determined, we will feedback the data to the corresponding department
and solve the problem.
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LVS
Questions
1.
What should a customer do if a resistor in the layout is not recognized
by UMC's LVS command file?
Some resistors that are customer made cannot be recognized in our
official LVS command files. In these cases, DS can provide help
to create a customized command file by customers' request.
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2.
How to compile a net_list with parameters on the sub_circuit line
by Dracula?
Simply add command ".PARAM" before the circuit description
block in the SPICE/CDL net_list file will have Dracula take the
parameters on the sub_circuit.
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3.
Why are some devices not recognized by LVS command file downloaded
from the UMC website?
LVS files are provided as working templates. Some modification may
be required for additional customized devices or recognition / construction
issue.
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4.
Are special components for mixed-mode and RF such as inductors and
triple-well MOS recognized by UMC's LVS command files?
Yes, these devices are supported in LVS files of UMC Mixed Mode/RFCMOS
process if FDK PCELL include them.
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5.
What is the LVS QA flow in UMC ?
1. LVS test structures
2. QA check list file.
3. Single device QA pattern.
4. Library and FDK circuit.
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6.
What is the UMC device naming rule?
Please reference UMC document:
GG-T20-003-E ( Model Card Naming Rule)
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