There is a critical need for SoC design acceleration techniques capable
of meeting the challenges created by accelerating time-to-market cycles.
Increased design risk, compressed design cycles and the threat of
cost overruns in both design and manufacturing has heightened the
urgency for identifying and correcting potential problems early in
the physical design cycle.
What you will learn:
Learn more about the UMC and Cadence digital reference flow. This
RTL-to-GDSII reference flow, being proven in silicon, is based on
the Cadence Encounter digital IC design platform and is the first
digital reference flow announced between the two companies. It takes
advantage of UMC's leading 130nm technology that offers Fusion,
an option that allows both high speed and low leakage transistors
to be combined onto a single chip ideal for wired and wireless applications.
Due to increasing interdependencies between design and manufacturing
at 130nm and below there has been more emphasis on integrated product
development. Mutual customers can use this reference flow to achieve
a predictable path to silicon, improve design productivity and avoid
silicon re-spins.
Who should attend
Design Managers and Engineers
Speaker(s)
Tim Decker, SP&R CoreComp Manager, Cadence Design Systems
Stanley Yeh, UMC
Resources
UMC
- Cadence data sheet
To learn more about the UMC-Cadence digital reference flow, and
how it can help you, please attend our free webcast on Tuesday,
October 5 from 9:00 – 10:00am PST.
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