Design
and Tape-out
UMC's quality practices include the implementation of Failure
Mode and Effect Analysis (FMEA) to ensure each customer's design
success. This methodology identifies key milestones to target
- including tape out success, timely wafer out, and fast production
ramp-up. Key deliverables and gating items are assessed through
criteria that range from Design Support Manual (DSM) readiness,
device performance, and IP availability to reliability and package
solutions. Resources are then committed and prepared to address
each element so that a complete follow-through of the plan can
be executed.
To ensure designs are built upon a robust process platform,
UMC has also designed dedicated test vehicles for various
process technologies. The vehicles include sophisticated VLSI
designs such as RISC CPU, embedded memory, and parametric
test structures. Design support for DFM and scan diagnostics
implementation deliver accelerated first silicon verification
and stable long-term yield.
UMC also performs a complete product tape-out review based
on a comprehensive checklist, which includes items such as
DRC and IP sanity check to reduce tape-out uncertainty.
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