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Design
and Tape-out
UMC's quality practices include the implementation of Failure
Mode and Effect Analysis (FMEA) to ensure each customer's
design success. This methodology identifies key milestones
to target - including tape out success, timely wafer out,
and fast production ramp-up. Key deliverables and gating items
are assessed through criteria that range from Design Support
Manual (DSM) readiness, device performance, and IP availability
to reliability and package solutions. Resources are then committed
and prepared to address each element so that a complete follow-through
of the plan can be executed.
To ensure designs are built upon a robust process platform,
UMC has also designed dedicated test vehicles for various
process technologies. The vehicles include sophisticated VLSI
designs such as RISC CPU, embedded memory, and parametric
test structures. Design support for DFM and scan diagnostics
implementation deliver accelerated first silicon verification
and stable long-term yield.
UMC also performs a complete product tape-out review based
on a comprehensive checklist, which includes items such as
DRC and IP sanity check to reduce tape-out uncertainty.
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Pilot
Run Success
To achieve pilot success in a timely fashion, UMC provides a
variety of Design for Diagnosis (DFD) and product functional
verification services that form a systematic approach to pilot
silicon verification. The capabilities include scan diagnostics,
IDDQ, bitmapping, and failure analysis.
Figure 1. UMC's Design for Diagnostic (DFD) service flow is
designed for fast yield ramp, as efficient analysis of silicon
data is imperative for timely product introduction.
UMC's system architecture knowledge enables rapid product debugging
and functionality check to accelerate first silicon verification.
Moreover, UMC's Fast Yield Feedback System offers real-time
data feedback and test data monitoring to dramatically reduce
the time to corrective action implementation.
Figure 2. Fast Yield Feedback System greatly improves cycle
time for data access.
The 24-hour online Engineering Data Analysis (EDA) System links
in-line measurement and CP mapping to speed yield learning and
analysis. The system features web tools capable of performing
customized analysis within yield results, including composition
map analysis to provide yield trend charts, bin map, and bin
summary.
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Production
Yield Ramp
UMC has developed a powerful and efficient
methodology for fast production yield ramp. Wafer sort data
is uploaded in real-time to UMC's database for analysis, allowing
corrective actions to be identified and implemented immediately.
Figure 3. Continuous yield enhancement converts
wafer sort electrical data into process defects for improvement.
Customers can maximize the benefits of this continuous
yield enhancement system by integrating the service with UMC's
Wafer Sort Service, resulting in faster cycle time and optimized
allocation of customers' engineering resources.
Figure 4. UMC's Integrated Wafer Sort Service delivers bottom-line
improvement. |
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