Development Methodology

Today's advanced process and package technologies pose challenges to SoC, SIP, and 3D-IC designers in terms of reliability, cost, and performance. UMC has partnered with industry-leading vendors to effectively address these challenges to offer customer benefits such as established and verified design rules, verification of low-k wafer materials and structures, optimized package materials and parameters, and enhanced reliability performance. Sophisticated test vehicles are another advantage achieved through UMC's methodology.

Customer endorsed qualification flows and specs

Verified Package Solution

UMC also works with world leading packaging houses to provide silicon proven packaging solutions. Starting from test-chip and technology development with assembly support through its packaging partners the silicon proven packaging solutions can meet the requirements of demanding designs, meet stringent qualification criteria, and ensure reliability for sophisticated chips such as those utilizing ultra low-k and low-k dielectric materials for Cu interconnect. All vendors are ISO9000 certified and must meet UMC set criteria regarding yields and cycle time.

* BOT : Bump On Trace

2.5D Interposer Solution

UMC has introduced the world’s first dedicated Open Ecosystem TSI Foundry Solution. We provide an open ecosystem model that includes the entire supply chain, and is ready for volume production. UMC has won an “Outstanding Performance Award” from one of our customers for production proven, mature and Excellent 2.5D Production Capability.

UMC Open Ecosystem Approach: Proven Open Ecosystem with Tier 1 OSAT using UMC 2.5D TSI wafer to Successfully Build an Open Ecosystem / Supply Chain

Test/Package Partners

UMC's major test and package subcontractors are located in Taiwan and throughout Asia. The close proximity of UMC's test and package partners to UMC's own facilities creates synergies that enable faster service and greater flexibility.