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UMC UNVEILS CHIPSIZER:
Online Tool Estimates Die Size and Silicon Cost
Foundry Provides Real-time Online "What-if" Analyses for
SOC Development
SUNNYVALE, Calif, October 30, 2000—UMC (NYSE:
UMC), a world leading semiconductor foundry, today introduced
Chipsizer, the first publicly available online tool that allows
designers and design managers to easily estimate die size
and silicon cost early in the product definition phase.
Marketing managers can work with their design team to add
and subtract product features and get instant feedback on
the impact on product cost. Users can access the tool
at www.umc.com
. Chipsizer is a
product of nTool, Inc., a Silicon Valley company.
Chipsizer enables users to create a graphical display of
their chip by selecting from an extensive menu of library
and IP elements (such as memory blocks input and output buffers,
microprocessor cores, soft cores, and PLLs) from UMC's Gold
IP™ catalog and entering other design information, such
as the number of random logic gates, customer-specific macros,
and pad types. Chipsizer then instantly generates a display
of the chip and estimated die size within the browser window.
The tool can also estimate gross die per wafer, net die wafer,
and die price when the user enters projected defect density
and wafer cost.
"Chipsizer is another important component of our e-Business
strategy that addresses a critical requirement for SOC designers,"
said Ed Wan, vice president of field engineering at UMC USA.
"We are helping them reduce time-to-market cycles by providing
a die size and cost estimation tool in an easy-to-use package,
from a reliable source. For the first time, everything needed
for silicon estimation is available online through the convenience
of a web browser."
Chipsizer allows users to add new features into their design
and see how they affect the die size. For I/O limited
designs, users can change the pad pitch or replace inline
I/Os with staggered I/O to see if that will reduce the die
size. Users can add a layer of metal and see if the
added wafer cost will be offset by the improved routing density
and therefore require a smaller die size. In addition,
users can migrate a design from 0.18-micron to 0.15-micron
technology to determine the affect on die size and cost.
"With Chipsizer, you can quickly do several 'what if'
scenarios and see which design options give the best result,"
said Ajay Shingal, vice president and general manager from
the Digital IC business unit at Tality. "It saves my
engineers the time and trouble of locating all the datasheets
from the numerous library and IP providers and from looking
up gate density and IP sizes. Most of the data needed is already
in Chipsizer."
Note From UMC Concerning Forward-Looking Statements
Some of the statements in the foregoing announcement are forward
looking within the meaning of the U.S. Federal Securities laws,
including statements about future outsourcing, wafer capacity,
technologies, business relationships and market conditions.
Investors are cautioned that actual events and results could
differ materially from these statements as a result of a variety
of factors, including conditions in the overall semiconductor
market and economy; acceptance and demand for products from
UMC; and technological and development risks.
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