UMC's 0.13-Micron Technology Enables Next Generation Semiconductor Applications with Innovative "Fusion" Design Option

First Foundry to Integrate High Speed and Low Power Transistors onto Single Chip Leveraging Industry's Only True Low-K Dielectric Material

SUNNYVALE, Calif., April 16, 2001--UMC (NYSE: UMC), a world leading semiconductor foundry, today announced that it is the first pure-play foundry to offer a process that combines high speed and low power logic transistors into one design, using its 0.13-micron technology that leverages the first and only dedicated foundry process that successfully integrates a true low-k dielectric material, at the 0.13-micron generation. This new logic process option, called Fusion, addresses the processor speed requirements of next-generation semiconductor products with the flexibility to simultaneously meet the most demanding power budgets.

"With this innovation of combining high-speed and low-power logic transistors into a single-chip design, we are offering chip designers an additional degree of freedom; the ability to integrate more functionality into a single design and thus enhance their ability to more readily introduce next-generation products," said Jim Ballingall, vice president of worldwide marketing for UMC. "Computing, communications and consumer applications can all benefit from the Fusion option, both wired and wireless, by alleviating the needs for cooling fans or exotic packages, and, of course, enabling longer times between battery recharges for portable applications."

Fusion is a subset of the logic offering of UMC's 0.13-micron technology. The technology enables a variety of design options to be seamlessly assembled together with logic in an SOC: analog and RF transistors, high-performance passive components (varactors, inductors, resistors) for analog and RF applications, and embedded DRAM and SRAM. The low-K material in UMC's 0.13-micron process provides a performance advantage of up to 30 percent over competing foundry processes for wire speed delay and power reduction.

Fusion Design Support and Availability
UMC is providing extensive design support for customers wishing to take advantage of its 0.13-micron Fusion option, including optimized design libraries and low-cost silicon verification. The high-speed standard cell library and memory compilers are available now from Virtual Silicon, with the Fusion standard cell library and memory compilers to be available in June. UMC's Silicon Shuttle? a program whereby customers can verify their advanced designs and prototypes in silicon and thus minimize risk and cost, with the Fusion option, is planned for availability in July of this year.

Mahesh Tirrupattur, vice president of Pacific Rim operations for Virtual Silicon said, "We are excited about extending our current UMC library offering to include 0.13-micron Fusion option. This provides IC designers with additional flexibility to execute their designs. With Fusion, high speed and low power considerations are no longer mutually exclusive."

Application Example: Next Generation Wireless IC's
UMC specified, developed, and production qualified 0.13-micron technology to address SOC applications "across the board" in computing, communication, and consumer markets. This breadth of applicability is realized by deploying multiple options for active and passive components, on a robust process technology platform. As an example, UMC's 0.13-micron technology provides an excellent solution for next-generation wireless handset applications where the digital baseband and analog intermediate frequency (IF) functions that are implemented into separate chips, in the current generation handsets, will now be combined into a single SOC; merging logic, analog, and embedded SRAM and DRAM memory. Within the logic section of this SOC, the Fusion option presents a compelling solution, as described below.

The baseband chips featured in low power mobile applications, such as the second-generation (2G) cell phones that are in common use today, use a single logic transistor optimized for low power consumption, which means speed is sacrificed to minimize power consumption. Third generation (3G) can't afford such compromise, as the 3G standards such as W-CDMA, are driving significantly higher performance requirements, with baseband processors that require several billion instructions per second (BIPS), while simultaneously continuing the demand for low power consumption to enable multi-hour "talk time" (voice, data transmission, etc.) between battery recharges. Fusion enables 3G applications to utilize the high-speed transistor for performance-intensive digital signal processing tasks such as web browsing, while functions where processor speed is not a stringent requirement (such as memory storage, control logic, accessories such as MP3 players, GPS, Imaging/Display functions, and Bluetooth extensions) can be relegated to the low power transistor, all on the same baseband IC.

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