Test Chip to Aid in Study of Multiple Threshold Voltages, Inductance Extraction and Other Signal Integrity Issues on 0.13 Micron and Below Process Technologies

MOUNTAIN VIEW, Calif., February 4, 2002 - Synopsys, Inc. (Nasdaq:SNPS), the technology leader for complex integrated circuit (IC) design, and UMC (NYSE:UMC), a world-leading semiconductor foundry, today announced they have taped out a test chip for researching signal integrity effects for designs developed in UMC's 0.13 micron Fusion process. The chip, dubbed ATG-SI, contains test structures that allow the study of multiple threshold voltages, inductance effects and model extraction. The chip also tests other signal integrity issues, including crosstalk and noise, which affect the performance and reliability of today's aggressive system-on-chip (SoC) designs. Both Synopsys and UMC are committed to addressing the needs of digital, analog, RF and mixed-signal designers who are targeting their designs to 0.13 micron and below copper process technologies.

"Analyzing and solving signal integrity problems in an SoC design are some of the toughest tasks in ultra-deep submicron technology," said Don MacMillen, vice president of Synopsys' Advanced Technology Group. "Synopsys and UMC will share the data with one another and apply the results to allow Synopsys to extend its EDA analysis and simulation solutions, and UMC to more readily target its deep submicron process technologies to today's most sophisticated designers."

Manufactured in UMC's 0.13 micron Fusion process, ATG-SI is a multi-purpose test chip that evaluates inductive coupling of global busses routed in the thick copper top layer using both standard driver-receiver pairs and differential on-chip signaling. The chip contains an expanded matrix of crosstalk capacitive coupling experiments to explore the impact of the timing differential between an aggressor and a victim's switching edges on the overall timing of each path. The chip is also used to evaluate the timing, leakage currents and switching currents of two blocks with identical functionality: one totally constructed from low-threshold voltage devices and the other synthesized using a combination of low- and high-threshold voltage devices. When design engineers use a high threshold library instead of a low threshold library, they sacrifice performance for lower leakage power. This chip allows designers to assess the trade off between performance and lower leakage power in order to compare simulated effects to real results for a desired outcome.

"As a leader in advanced process development and manufacturing, UMC is continuously looking for ways to make it easier to manufacture extremely complex and sophisticated designs," said Frank Wen, general manager and head of Central Research Development at UMC. "Partnering with Synopsys to address signal integrity issues will tremendously benefit our mutual customers as they move to 0.13 micron processes and below. Accordingly, we are looking forward to receiving the data from the test chip and applying it to our manufacturing processes."

About Fusion
UMC's 0.13 micron Fusion design option is the foundry industry's first process that allows both high-speed and low-leakage transistors to be integrated into a single IC. This allows designers to create chips that can meet vigorous high performance demands while still maintaining low power flexibility. UMC offers extensive design support for those wishing to design into the Fusion option, including optimized design libraries and low-cost silicon verification.

About Synopsys
Synopsys, Inc. (Nasdaq:SNPS), headquartered in Mountain View, California, creates leading electronic design automation (EDA) tools for the global electronics market. The company delivers advanced design technologies and solutions to developers of complex integrated circuits, electronic systems and systems on a chip. Synopsys also provides consulting and support services to simplify the overall IC design process and accelerate time to market for its customers. Visit Synopsys at http://www.synopsys.com.

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