Sidense to Deliver OTP Cores in UMC's 90nm and 65nm Process Nodes

OTP memory IP supplier to provide a path to cost reduction to SoC designers

OTTAWA, Canada, and HSINCHU, Taiwan, April 25th, 2006 - Sidense Corp., a provider of One-Time-Programmable (OTP) memory intellectual property (IP) and UMC (NYSE: UMC, TSE: 2303), a leading global semiconductor foundry, today announced that Sidense's 1T-fuseTM family of embedded OTP cores are slated to be silicon-verified in UMC 90nm and 65nm processes through UMC's IP Alliance Program and offered for use to system-on-chip (SoC) designers. The cores are scalable to UMC's CMOS processes without requiring additional mask or processing steps, providing users with shortened time-to-market and a path to cost reduction for their current and future designs.

The OTP cores are scalable across UMC's CMOS processes and easily ported across other technology nodes, such as 110nm and 80nm, potentially providing customers with several generations of continuous SoC migration. Sidense's high density macros can also be parameterized to obtain different configurations and can be used to replace external FLASH and EEPROM as well as a field programmable alternative to MASK ROM.

"As the demand for embedded OTP cores continues to increase, we are pleased to partner with a world leading foundry such as UMC," said Xerxes Wania, President and C.E.O. of Sidense Corp. "We continue to work with UMC to provide OTP solutions to customers looking for an OTP core targeted at low and high density applications. SoCs for printers, cameras, set-top boxes, mobile and handheld devices can benefit from the high density, secure and low power characteristics of Sidense's 1T-FuseTM OTP offering. "

In January, Sidense announced its OTP core targeted towards UMC's 130nm standard logic digital CMOS process (see http://sidense.com/index.php?option=com_content&task=view&id=22&Itemid=23&lang=ISO-8859-1).

"UMC's extensive IP portfolio has become a strong competitive advantage for customers designing today's sophisticated SoCs," said Ken Liou, director of the IP and Design Support division at UMC. "Sidense's technology is a welcome addition to our IP Alliance Program, as it will provide designers with a silicon proven OTP option for their 130nm, 90nm and 65nm designs."

About UMC
UMC (NYSE: UMC, TSE: 2303) is a leading global semiconductor foundry that manufactures advanced process ICs for applications spanning every major sector of the semiconductor industry. UMC delivers cutting-edge foundry technologies that enable sophisticated System-on-Chip (SoC) designs, including volume production 90nm, industry-leading 65nm, and mixed signal/RFCMOS. UMC's 10 wafer manufacturing facilities include two advanced 300mm fabs; Fab 12A in Taiwan and Singapore-based Fab 12i are both in volume production for a variety of customer products. The company employs approximately 12,000 people worldwide and has offices in Taiwan, Japan, Singapore, Europe, and the United States. UMC can be found on the web at http://www.umc.com.

About Sidense
Sidense Corp., focuses on developing Non-Volatile Memory (NVM) intellectual property (IP) cores to be embedded onto standard logic digital CMOS Application Specific Integrated Circuits (ASICs) and custom Integrated Circuits (ICs). Sidense's 1T-FuseTM technology is most suitable for feature sizes of 130nm and smaller. Potential applications include electrical fuse, FLASH and MASK programmable ROM replacement, code storage, RFID, Unique ID, encryption, key storage and in Digital Rights Management. They currently have offices in Mississauga and Ottawa, Canada. For further information regarding Sidense's products, please visit the website http://www.sidense.com.

Note From UMC Concerning Forward-Looking Statements
Some of the statements in the foregoing announcement are forward looking within the meaning of the U.S. Federal Securities laws, including statements about future outsourcing, wafer capacity, technologies, business relationships and market conditions. Investors are cautioned that actual events and results could differ materially from these statements as a result of a variety of factors, including conditions in the overall semiconductor market and economy; acceptance and demand for products from UMC; and technological and development risks.

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