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UMC Releases 65nm DFM Design Enablement
Kit
New DEK offers fabless
semiconductor customers comprehensive support for leading EDA vendors'
DFM tools
HSINCHU, Taiwan - December 11, 2007 -
UMC (NYSE: UMC; TSE: 2303), a leading global semiconductor foundry,
today announced the release of its comprehensive all-in-one 65nm
design for manufacturing (DFM) support package. The new DFM Design
Enablement Kit (DEK) encompasses all the models required by qualified
model-based DFM tools that support UMC's 65nm process technology.
The company collaborated with leading EDA vendors to develop the
DEK in order to provide an easy to use DFM solution for its 65nm
customers.
"It is well known that IC designs produced
at the 65nm node and below face multiple production challenges such
as increasing process variations and rapidly diminishing printability,
which often lead to undesirable manufacturing yields and unacceptable
performance variations," said Patrick T. Lin, head of worldwide
IP development and design support at UMC. "To help designers
offset their 65nm production challenges, UMC has been closely collaborating
with the industry's leading EDA vendors to successfully deliver
optimal DFM solutions."
UMC's DEK package consists of 65nm DFM solutions
in three main areas:
Critical Area Analysis (CAA): users can perform critical area
optimization such as wire spreading and widening with encrypted
defect density data to improve Defect-Limited Yield (DLY).
Chemical Mechanical Polishing (CMP): with CMP thickness analysis,
CMP simulation based on the advanced CMP model determines thickness
variation and compensates with timing driven metal fill.
Lithography Simulation Check (LSC): the tool analyzes impact from
different layout practices and identifies potential lithography
hotspots using lithography simulation tools with the encrypted technology
data.
Based on robust and silicon-validated models,
the DEK offers comprehensive support for leading DFM tools, both
in platform-based solutions and in alternative design flows by mixing
and matching EDA tools from different vendors. The package includes
a user friendly graphical user interface (GUI) for easy setup of
a DFM design database, completed with application notes and qualification
reports for design reference. The application note demonstrates
how the tools can be deployed in various design flows. The qualification
report shows the accuracy and effectiveness by comparing the tool's
prediction correlated with proven silicon data.
"The DEK is the newest addition to our comprehensive
DFM support for leading edge process technology. It's a testimony
to our commitment to deliver our customers the foundry industry's
most comprehensive and user friendly DFM solutions," said Garry
Shyu, director of design tool & DFM support, system & architecture
support at UMC.
Partner Quotes
"The UMC DEK is an ideal interface between Cadence's model-based,
variation-aware DFM solution and a 65nm foundry process," said
Nitin Deo, group director of DFM marketing at Cadence. "The
UMC DEK provides easy access to Cadence's fast lithography estimation
and industry-leading physical, electrical, CMP and timing analysis
DFM technologies, closing the loop for designers seeking effective
yield-enhancing DFM solutions."
"Magma supports the qualified DFM DEK approach
of UMC in its TalusTM, Blast and QuartzTM products. Utilizing the
DEK we are able to address the areas of critical-area analysis,
CMP and litho hot-spot correction during implementation and at final
tapeout," said John Lee, general manager of Magma's Physical
Verification Business Unit. "This approach combines UMC's process
information with Magma's implementation and sign-off tools, and
gives customers the best solution for designing at 65nm. We're confident
that this solution will relieve the concerns that customers may
have regarding manufacturability issues relating to design and allow
them to produce products with better yield and performance."
"We are pleased to work with UMC to ensure
our customers have access to accurate DFM tools optimized for UMC's
manufacturing process," said Joe Sawicki, vice president and
general manager, Design to-Silicon Division, Mentor Graphics. "UMC
customers who use Calibre for signoff can also use our integrated
DFM tools that work seamlessly with UMC's encrypted DFM models to
improve their yield."
"We are glad that our full chip DFM-fix
tool AcumaTM has been qualified in UMC's DEK through our mutual
customers," said by Yongbo Jia, president of Nannor Technologies,
Inc. "DFM fix emerges as a valuable step for SoC designs at
65nm and below. Based on our patented technologies, Acuma provides
designers a full chip post layout optimization solution with unparalleled
capacity and speed for manufacture closure, while retaining timing,
signal integrityand power closure. Acuma can be seamlessly integrated
with mainstream EDA design flows, including Cadence, Magma, and
Synopsys."
"Our collaboration with UMC through Ponte's
Building BridgesTM Partner Program continues to benefit our mutual
customers," said Michael Buehler-Garcia, vice president of
marketing and business development, Ponte Solutions. "Today's
announcement expands our mutual efforts, giving 65nm designers the
capability to custom tune their designs, thereby gaining the maximum
value from UMC's 65nm offering."
"As design for new technology nodes become
more complex and the need for first-pass silicon success increases,
DFM innovation is a vital component in enabling customers to meet
their design schedules and yield expectations," said Rich Goldman,
vice president of strategic market development at Synopsys. "Through
our strategic relationship with UMC, focused on the DFM flow and
tools for yield analysis and enhancement, Synopsys is helping UMC
to provide proven DFM solutions to address our joint customers'
needs."
Availability
The DEK package from UMC currently supports leading EDA tools from
Cadence Design Systems, Magma Design Automation, Mentor Graphics,
Nannor Technologies, Ponte Solutions, and Synopsys. It is immediately
available upon request through UMC's customer service or design
support departments.
Note From UMC Concerning Forward-Looking Statements
Some of the statements in the foregoing announcement are forward
looking within the meaning of the U.S. Federal Securities laws,
including statements about future outsourcing, wafer capacity, technologies,
business relationships and market conditions. Investors are cautioned
that actual events and results could differ materially from these
statements as a result of a variety of factors, including conditions
in the overall semiconductor market and economy; acceptance and
demand for products from UMC; and technological and development
risks.
About UMC
UMC (NYSE: UMC, TSE: 2303) is a leading global semiconductor foundry
that manufactures advanced system-on-chip (SoC) designs for applications
spanning every major sector of the IC industry. UMC's SoC Solution
Foundry strategy is based on the strength of the company's advanced
technologies, which include production proven 90nm, 65nm, mixed
signal/RFCMOS, and a wide range of specialty technologies. Production
is supported through 10 wafer manufacturing facilities that include
two advanced 300mm fabs; Fab 12A in Taiwan and Singapore-based Fab
12i are both in volume production for a variety of customer products.
The company employs approximately 13,000 people worldwide and has
offices in Taiwan, Japan, Singapore, Europe, and the United States.
UMC can be found on the web at http://www.umc.com.
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UMC
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KJ Communications
Eileen Elam
(408) 927-7753
eileen@kjcompr.com
In Taiwan:
UMC
Alex Hinnawi
(886) 2-2700-6999 ext. 6958 |
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