Sunnyvale, Calif. - January 25, 1999 - UMC Group today announced that it is engaging with customers for 0.18-micron foundry services. The announcement heralds the availability of design kits and physical designs for 0.18-micron libraries customized to UMC Group's 0.18-micron process technology.

The customized libraries cover standard cells, I/Os, and memory compilers for the UMC Group Gold LogicTM L180 process. They are available free-of-charge to the customer from Artisan Components and Mentor Graphics, and allow designers to begin their 0.18-micron designs today. These are the first 0.18-micron libraries to be available free-of-charge to foundry customers, and the only ones to offer free technical support directly from the library vendor.

"UMC Group is clearly taking the leadership role for 0.18-micron foundry services. We were the first to deliver 0.18-micron functional prototypes, the first to deliver free 0.18-micron libraries, and the only foundry to have a 0.18-micron test-chip program available at a nominal charge to customers. Our early collaboration with the leading names in the library, IP, and EDA tool community is evidence that we are widely recognized within the industry for our accomplishments in technology development and very deep sub-micron foundry services," said Jim Kupec, president of UMC Group (USA).

In addition to its library program, UMC Group has joint-development projects to deliver silicon-verified extraction files with Avant!, Mentor, Simplex and Synopsy for the L180 process. These will greatly increase the probability that complex SOC designs achieve first time working silicon. UMC Group also provides customers with a comprehensive catalog of IP that addresses the cost and time-to-market concerns of designers for UMC Group's 0.18-micron technology. Many of these IP mega-cell blocks are available at deep discounts exclusively to UMC Group customers.

Jim Kupec continued, "For the first time, fabless semiconductor companies can compete head-to-head with industry giants in terms of production technology capabilities, and the free-of-charge libraries remove a significant barrier that faces IC design houses with limited resources and pressing time-to-market concerns. We believe that there will be a strong demand for 0.18-micron capacity, and we see the crossover from 0.25 to 0.18-micron technology, from a cost perspective, happening early in the year 2000. Since complex system-on-chip (SOC) designs require one year or more to complete, the availability of libraries and tools today will allow a wide range of customers to begin their designs in time to maximize profits."

The Silicon Shuttle test chip program is a critical piece in UMC Group's 0.18-micron foundry solution. It is the primary program for silicon verification for the L180 process. Customers tape-out their 0.18-micron prototypes at a nominal charge, greatly reducing their risk by allowing pre-production silicon verification. UMC Group is the only foundry to offer this type of service for 0.18-micron. The Silicon Shuttle is also offered free-of-charge to IP and Library vendors wishing to make their products available to UMC Group foundry customers. The first 0.18um Silicon Shuttle test wafers taped-out in Q4 1998 carrying test chips for a wide range of applications including graphic chips, CPUs and FPGAs. The next Silicon Shuttle will tape-out soon.

Perhaps the most reassuring aspect of UMC Group's 0.18-micron process, from a customer perspective, is the fact that it has already been proven in test production. Leading fabless companies, including S3 and Xilinx, have worked in close coordination with the UMC Group Technology Development Department to produce chips using the L180 process. UMC Group has delivered these chips, and functional prototypes have already been characterized.

UMC Group will ramp volume production for the L180 process in late March. The performance of the L180 process will be further enhanced by the incorporation of UMC Group's Dual Damascene Copper interconnect and Low-K dielectric technology in Q3 1999.