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DESIGN AUTOMATION CONFERENCE, Anaheim, Calif. - June 9, 2008 Extreme DATM, a leading provider of new-generation integrated circuit (IC) performance and yield improvement solutions, and UMC (NYSE: UMC, TSE: 2303), a leading global semiconductor foundry, announced their collaboration on variation-aware IC design flows for 65nm and finer process technologies. The flows reduce design uncertainty and predict design performance and yield, by analyzing timing behavior in the presence of process variations. The first flow, based on the Extreme Gold™ statistical analysis suite, has already been applied to a test-chip at UMC's 65nm process node. This collaboration builds on previous cooperation for the 90nm node.
The current 65nm partnership includes collaborative efforts in the following areas:
- Characterization of UMC libraries for global and mismatch variations to analyze these effects
- Location-based on-chip variation (LOCV) model construction for improved accuracy of variation analysis
- Variation-aware extraction and timing analysis on a 65nm test chip.
Mutual customers of UMC and Extreme DA will experience improved parametric yield, and reduced pessimism, and optimized performance for ICs produced in UMC's proven 65nm process through the capabilities of the Extreme Gold suite.
"UMC is continually striving to improve parametric yield prediction and performance optimization capabilities for our customers," said Darsun Tsien, UMC's vice president of design methodology. "The Extreme Gold statistical analysis suite has demonstrated its capability in the timing analysis and modeling of on-chip process variations. We look forward to offering the benefits of these new design flows to our 65nm customers."
Extreme DA CEO, Mustafa Celik, said, "We are honored that UMC, one of the world's top foundries is continuing to develop these unique, variation-aware design and timing flows for advanced systems-on-chips (SoCs). We expect that they will satisfy the fabless semiconductor companies' demands for faster, more accurate timing closure and higher chip yields."
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