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Design Flow Reference

Given the deep sub-micron design challenges that circuit designers are facing, UMC Reference Design Flows provide customers with EDA design methodologies that reduce time-to-market by enabling manufacturability. The UMC Reference Design Flows incorporate 3rd-party EDA vendor's baseline design flows to address issues such as timing closure, signal integrity, power consumption and design for manufacturability and adopt a hierarchical design approach built upon silicon validated process libraries. The UMC Reference Design Flows cover from RTL coding all the way to GDS-II generation and support Cadence, Magma, Mentor and Synopsys EDA tools. All of these tools have been correlated to UMC silicon and can be interchanged for added flexibility.

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Key Benefits to Customers

The UMC Reference Design Flows minimize or eliminate any library, technology, tool and flow issues prior to customers' using the libraries, PDK/Foundry Design Kits (FDK) or tools in their design process and predict how their silicon really behaves. In brief, it significantly shortens :

Time to Tape out

Time to Market

Time to Volume