聯華電子與美商益華電腦 (Cadence Design Systems, Inc.) 今日 (25日) 共同宣佈，聯華電子針對 X Architecture 晶片設計的65奈米製程技術已經準備就緒。益華電腦與聯華電子已經成功驗證 65 奈米 X Architecture 設計規則，Cadence® X Architecture 以及設計支援手冊 (DSM) 文件，使得無晶圓廠設計公司與整合元件廠可以將 X Architecture 低成本與高效能的優點，應用在他們先進的系統單晶片設計上。聯華電子與益華電腦將在先進製程上，為雙方的客戶提供 X Architecture 設計生產。

“多年來聯華電子與益華電腦合作，將 X Architecture 的優勢提供給主流系統單晶片設計公司使用，”聯華電子系統架構支援部門林子聲總工程師表示。“我們非常高興可以將這項技術拓展至 65 奈米製程，因此我們的客戶現在可以利用業界最先進的製程與 X Architecture 的優勢，增加他們產品的競爭力。”

聯華電子是第一個加入 X Initiative 的純晶圓專工公司，並且也是第一家宣佈可於 0.13 微米與 90 奈米製程接受 X Architecture 晶片投片生產的公司。

“益華電腦與聯華電子承諾將支援後端使用者在設計上的需求，並且協力合作，以確保 X Architecture 的基礎設計架構支援能擴展至聯華電子的 65 奈米製程上，”益華電腦 X Architecture 副總裁兼總經理 Kalyan Thumaty 先生表示，“益華電腦的 X Architecture 針對今日極具挑戰性的成本、效能以及功率需求，提供了設計上的最佳解決之道。聯華電子的 65 奈米製程技術，結合益華電腦的 X Architecture，能在設計複雜的系統單晶片時，為雙方共同的客戶提供獲得競爭優勢的方法。”

聯華電子的 0.13 微米、90 奈米以及 65 奈米製程上，目前都已提供益華電腦的 X Architecture 予客戶使用。

The X Architecture represents an innovative approach for orienting a chip's microscopic interconnect wires, with the pervasive use of diagonal routes in addition to traditional right-angle "Manhattan" routing. The X Architecture can provide significant improvements in chip area, performance, power consumption and cost, by enabling designs with significantly less wirelength and fewer vias (the connectors between wiring layers).

Cadence enables global electronic-design innovation and plays an essential role in the creation of today's integrated circuits and electronics systems. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, printed-circuit boards and systems used in consumer electronics, networking and telecommunications equipment, and computer systems. Cadence reported 2005 revenues of approximately $1.3 billion, and has approximately 5,000 employees. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.

Note From UMC Concerning Forward-Looking Statements
Some of the statements in the foregoing announcement are forward looking within the meaning of the U.S. Federal Securities laws, including statements about future outsourcing, wafer capacity, technologies, business relationships and market conditions. Investors are cautioned that actual events and results could differ materially from these statements as a result of a variety of factors, including conditions in the overall semiconductor market and economy; acceptance and demand for products from UMC; and technological and development risks.