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Package Solution Development

Development Methodology

Today's advanced process and package technologies pose challenges to SoC, SIP, and 3D-IC designers in terms of reliability, cost, and performance. UMC has partnered with industry-leading vendors to effectively address these challenges to offer customer benefits such as established and verified design rules, verification of low-k wafer materials and structures, optimized package materials and parameters, and enhanced reliability performance. Sophisticated test vehicles are another advantage achieved through UMC's methodology.

Customer endorsed qualification flows and specs

Verified Package Solution

UMC also works with world leading packaging houses to provide silicon proven packaging solutions. Starting from test-chip and technology development with assembly support through its packaging partners the silicon proven packaging solutions can meet the requirements of demanding designs, meet stringent qualification criteria, and ensure reliability for sophisticated chips such as those utilizing ultra low-k and low-k dielectric materials for Cu interconnect. All vendors are ISO9000 certified and must meet UMC set criteria regarding yields and cycle time.



Technology node

14nm & above Availability

Wire Bond (BOAC)

Wire

Au / Cu / Ag

Diameter

0.6 / 0.7 mil

Pitch

40 / 45µm

Bump / Flip Chip

Bump

EU / SnAg

Cu Pillar

Au

Pitch

130µm

60~130µm

18µm

Structure

BOT* / BGA / CSP/ WLP

* BOT : Bump On Trace

Test/Package Partners

UMC's major test and package subcontractors are located in Taiwan and throughout Asia. The close proximity of UMC's test and package partners to UMC's own facilities creates synergies that enable faster service and greater flexibility.

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