SUNNYVALE, Calif., April 9, 2001 - United Microelectronics Corp. (NYSE: UMC), Synopsys, Inc. (Nasdaq:SNPS), and Virtual Silicon today announced that, through their ongoing collaborative efforts, customers have a new alternative for getting their designs to tape out, and therefore final production, more quickly. UMC customers can now use Synopsys' Physical Synthesis, a proven methodology for solving timing closure challenges, with physical IP from Virtual Silicon targeted towards UMC process technologies. The UMC 0.13-micron libraries with Synopsys' Physical Compiler views will be available from Virtual Silicon in Q2' 2001. The 0.18- and 0.15-micron libraries will also be ready for download from Virtual Silicon's web site in the same time frame.

"We are constantly looking at new approaches to enable our customers to get to silicon faster and accordingly have collaborated with Synopsys and Virtual Silicon to create solutions for our joint customers," said Edward Wan, vice president of worldwide field engineering at UMC. "Virtual Silicon has been helping with this effort by creating libraries that enable EDA tools and IP to target our fabs."

"We are very pleased that UMC is supporting the Synopsys' Physical Synthesis methodology with Virtual Silicon libraries. UMC is the first foundry vendor to announce support for our physical synthesis tools," said Sanjiv Kaul, senior vice president and general manager of Synopsys' Physical Synthesis business unit. "Some of our joint customers have already taped out with UMC and with this announcement we expect many more customer successes. Synopsys' Physical Synthesis is the leading timing closure solution with support from multiple semiconductor vendors."

"Our customers have been achieving excellent results with Synopsys' Physical Synthesis and our eSi-Route libraries for UMC," said Taylor Scanlon, president and CEO of Virtual Silicon. "We are committed to support Synopsys' Physical Synthesis tools with our Silicon Ready IP to provide the accurately modeled timing and placement solutions required by today's leading-edge SOC designers that utilize UMC's fabs."

Pioneered by Synopsys, Physical Synthesis helps designers address the challenges of implementing next-generation system-on-a-chip designs. Synopsys' overall design flow includes Chip Architect design planner, Physical Compiler unified synthesis and placement, and FlexRoute top-level router. Synopsys' Physical Synthesis leverages industry-standard tools such as Design Compiler, Module Compiler, PrimeTime Power Compiler and DFT Compiler. Proven interfaces to third-party solutions allow the products to easily plug into an existing design flow.

Synopsys, Inc. (Nasdaq:SNPS), headquartered in Mountain View, California, creates leading electronic design automation (EDA) tools for the global electronics market. The company delivers advanced design technologies and solutions to developers of complex integrated circuits, electronic systems, and systems on a chip. Synopsys also provides consulting and support services to simplify the overall IC design process and accelerate time to market for its customers. Visit Synopsys at http://www.synopsys.com.

Virtual Silicon Technology is a leading supplier of embedded semiconductor technology to manufacturers and designers of complex systems-on-chip. The company provides process-specific embedded components including standard cell libraries, I/Os, SRAM compilers, mixed-signal functions, PLL compilers and embedded Flash/EEPROM solutions. Customers include leading semiconductor manufacturers and foundries, ASSP designers, and systems-on-chip developers who demand the highest quality, maximum performance, lowest power and optimum densities for their semiconductor innovations. For more information on Virtual Silicon Technology and its products contact Mahesh Tirupattur at (408) 548-2756, email address: mahesh@virtual-silicon.com or go to www.virtual-silicon.com Note From UMC Concerning Forward-Looking Statements

Some of the statements in the foregoing announcement are forward looking within the meaning of the U.S. Federal Securities laws, including statements about future outsourcing, wafer capacity, technologies, business relationships and market conditions. Investors are cautioned that actual events and results could differ materially from these statements as a result of a variety of factors, including conditions in the overall semiconductor market and economy; acceptance and demand for products from UMC; and technological and development risks.

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Synopsys is a registered trademark of Synopsys, Inc. Physical Compiler, Design Compiler, Module Compiler, and Power Compiler are trademarks of Synopsys, Inc. Virtual Silicon, eSi-Route and Silicon Ready are trademarks of Virtual Silicon Technology. All other trademarks or registered trademarks mentioned in this release are the intellectual property of their respective owners.