UMC is the foundry leader in 65nm process technology, having delivered the foundry industry's first 65nm customer products in June of 2005. UMC's 65nm technology supports high performance (65SP) and low power (65LL/65LP) requirements.

65nm Technology Offering

UMC's 65-nanometer SoC solution begins with a flexible technology design platform. Customers are able to choose the process device options that are optimized for their specific application, such as Standard Performance (SP), Low Leakage (LL) or Low Power (LP) transistors. The high performance characteristics of UMC's 65nm SP process enable designers to utilize the technology to power a broad range of applications from consumer products to graphics ICs. Technology options can also be implemented including mixed signal/RFCMOS and embedded memories (1T-RAM URAM^TM Option, 0.12um²) to further customize the process.

UMC's Value Driven 65nm Technology

Compared to 90nm, UMC's 65nm can improve gate delay from 30% to 50% at similar leakage levels. Mass production 65nm ICs at UMC include customer products that utilize advanced dual gate oxide structures with up to 10 different metal layers.

UMC's 55nm standard performance process (55SP) is a 90% shrink from the 65nm node (65SP), providing customers with smaller die size while maintaining the same performance with similar or lower power. In addition to this standard performance platform (55SP), we also provide a Low Power platform (55LP) option that is compatible with the industry standard process. Both of these platforms are ready for customer design-in.