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HSINCHU, Taiwan, May 19, 2004 - UMC (NYSE: UMC; TSE: 2303), a world leading semiconductor foundry, today announced that its research and development team has achieved a significant performance enhancement on 45nm p-channel transistors through substrate engineering. UMC's engineers have implemented a new substrate crystalline orientation scheme to realize a transistor drive current increase of 30%, compared to devices fabricated on silicon substrates with conventional surface orientation. Performance gain is based on the same level of device leakage.
"One major focus of device development is on finding 'mobility enhancement' techniques that could maintain performance gain without deteriorating device leakage" said Dr. Kuan Liao, Director UMC's Exploratory Technology Division of Central Research and Development. "This achievement increases our options among other frequently discussed device improvements such as strained silicon, high-k gate dielectrics, and silicon on insulator (SOI) that UMC is also exploring in parallel."
A 70% hole mobility gain was demonstrated with this new substrate engineering, which accounted for the 30% increase in PMOS drive current. In addition to the performance gain, improved distribution of device parameters was exhibited, indicating the increased potential for future manufacturability of this technology. Moreover, the improved noise characteristics make this method suited for analog applications.
The details of this technology finding will be reported in the upcoming Symposia on VLSI Technology and Circuits to be held at Honolulu, Hawaii in June 15-17, 2004.
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