HSINCHU, Taiwan and SAN JOSE, Calif. - May 25, 2006 - UMC (NYSE: UMC, TSE:2303), a leading global semiconductor foundry, and Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced the readiness of UMC's 65nm process technology for X Architecture-based chip designs. Cadence and UMC have successfully qualified 65nm X Architecture design rules, the Cadence® X Architecture, and Design Support Manual (DSM) documents, allowing fabless and IDM companies to leverage the cost and performance benefits of the X Architecture for their leading system-on-chip (SoC) designs. The two companies are engaging with mutual customers towards X Architecture production designs at leading process nodes.

"UMC has been working with Cadence for several years to bring the advantages of the X Architecture to mainstream SoC designers," said Patrick T. Lin, chief SoC architect at UMC. "We are delighted to extend our readiness of this technology to the 65nm generation, as leading customers can now leverage the X Architecture with the industry's most advanced process technology to increase the competitiveness of their products."

UMC became the first pure-play foundry to join the X Initiative, as well as the first to announce its readiness to accept X Architecture-based designs for fabrication at 130nm and 90nm process nodes.

"Cadence and UMC are committed to supporting end-user design needs and have collaborated to ensure design infrastructure readiness to extend support for the X Architecture to UMC's advanced 65nm process," said Kalyan Thumaty, vice president and general manager of X Architecture at Cadence. "The Cadence X Architecture provides a powerful way to optimize designs for today's challenging cost, performance and power needs. UMC's 65nm process, together with the Cadence X Architecture, offers our common customers an avenue to gain a strong competitive advantage when designing their sophisticated SoCs."

The Cadence X Architecture is now available to customers for UMC's 130nm, 90nm and 65nm process technologies.

The X Architecture represents an innovative approach for orienting a chip's microscopic interconnect wires, with the pervasive use of diagonal routes in addition to traditional right-angle "Manhattan" routing. The X Architecture can provide significant improvements in chip area, performance, power consumption and cost, by enabling designs with significantly less wirelength and fewer vias (the connectors between wiring layers).

Cadence enables global electronic-design innovation and plays an essential role in the creation of today's integrated circuits and electronics systems. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, printed-circuit boards, and systems used in consumer electronics, networking and telecommunications equipment, and computer systems. Cadence reported 2005 revenues of approximately $1.3 billion, and has approximately 5,000 employees. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.

UMC (NYSE: UMC, TSE: 2303) is a leading global semiconductor foundry that manufactures advanced process ICs for applications spanning every major sector of the semiconductor industry. UMC delivers cutting-edge foundry technologies that enable sophisticated system-on-chip (SoC) designs, including 90nm copper, 0.13um copper, and mixed signal/RFCMOS. UMC is also a leader in 300mm manufacturing; Fab 12A in Taiwan and Singapore-based UMCi are both in volume production for a variety of customer products. UMC employs over 10,500 people worldwide and has offices in Taiwan, Japan, Singapore, Europe, and the United States. UMC can be found on the web at http://www.umc.com.

Note From UMC Concerning Forward-Looking Statements
Some of the statements in the foregoing announcement are forward looking within the meaning of the U.S. Federal Securities laws, including statements about future outsourcing, wafer capacity, technologies, business relationships and market conditions. Investors are cautioned that actual events and results could differ materially from these statements as a result of a variety of factors, including conditions in the overall semiconductor market and economy; acceptance and demand for products from UMC; and technological and development risks.

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