Palo Alto, Calif. and Hsinchu, Taiwan, July 6, 2006 - Extreme DATM, a provider of next generation variation-aware integrated circuit (IC) design and sign-off solutions, and UMC, a leading global semiconductor foundry, announced their collaboration on variation-aware IC design flows for 90-nm and lower process technologies. The flows aim to accelerate time-to-manufacturing and reduce design uncertainty by focusing on design-for-manufacturing (DFM) issues such as timing and power variability prediction and optimization in the presence of process variations. The first flow, based on Extreme DA's production-ready Extreme XTTM sign-off tools, has already been applied to a UMC test-chip at UMC's 90-nm process node.
The partnership between Extreme DA and UMC focuses on 65-nm design flow development, including:
- Design of test structures for collecting specific process variation data
- Extraction of pure random, spatially-correlated random, die-to-die random, and systematic variations in the front- and Backend processes
- Silicon verification of XT's statistical timing and extraction results.
Using Extreme XT's statistical extraction and timing tools will allow mutual customers to utilize this unique variation-aware sign-off capability on UMC's proven 65-nm process, enabling improved parametric yield, reduced pessimism, and robust design capabilities.
"Our engineers continue to explore and develop ways to help our customers better achieve parametric yield prediction and optimization for a robust design closure," said Patrick T. Lin, chief SOC architect at UMC. "Extreme DA's IC design and sign-off tools provide a valuable resource to help them realize this goal. Our collaboration with Extreme DA has produced very encouraging results. We look forward to offering the benefits of these design flows to our 90-nm and 65-nm customers in the near future."
Extreme DA CEO, Mustafa Celik, said, "It has been a pleasure to work closely with one of the world's top foundries to develop these unique, variation-aware design and sign-off flows for advanced systems-on-chips (SoCs). We expect that they will satisfy the fabless semiconductor companies' demands for faster, more accurate timing closure and higher chip yields."
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