SAN JOSE, Calif. and HSINCHU, TAIWAN, Nov. 6, 2006 - Cadence Design Systems, Inc. (NASDAQ:CDNS), the leader in global electronic-design innovation, and leading global semiconductor foundry UMC (NYSE: UMC, TSE: 2303) today announced the success of their RF integrated-circuit design and verification on a co-developed wireless system-on-chip (SoC) reference flow. The flow, featuring the Cadence QRC Extraction and the Virtuoso UltraSim Full-chip Simulator, combines the Cadence Virtuoso custom design platform and UMC's RFCMOS process to deliver silicon-accurate chip simulation and verification flows.

UMC and Cadence announced their alliance to streamline wireless design for the fabless market on October 6, 2005. Since then, UMC has successfully produced a test chip that verifies the Cadence QRC Extraction technology. The Cadence Virtuoso UltraSim provided UMC with transistor-level transceiver simulation, which reduced the verification cycle time by half. UMC and Cadence worked closely together to develop a methodology and flow to verify post-layout transistor-level full-chip transceivers, by combining UMC's 0.13um MM/RF PDK validated for the Virtuoso platform, silicon-accurate Cadence QRC Extraction technology, and the Virtuoso UltraSim.

"Designers building SoCs for wireless applications can gain a competitive advantage when they use Virtuoso combined with UMC's RFCMOS process," said Patrick Lin, chief SoC architect at UMC. "For back annotation verification, Cadence QRC Extraction provides a convenient and accurate methodology to predict the performance in critical building blocks such as LC-tank VCO. Further, the extraction that covers RLCK can be used to predict with greater accuracy the frequencies and how the design will perform in silicon. These benefits and our alliance with Cadence have resulted in a seamless design environment for the analog/RF design communities."

The continually increasing demand for feature-rich wireless devices with complex functionality and minimized area and power requirements is driving the need for silicon-accurate parasitic extraction and transistor-level full-chip simulation flows that reduce risk and time-to-market for custom wireless SoCs.

"Cadence and UMC are working side-by-side to drive and deliver integrated, low-cost, high-performance, low-power wireless SoC solutions to our mutual customers," said Charles Giorgetti, corporate vice-president, Product Marketing, at Cadence. "By collaborating with UMC, we are able to provide a silicon-validated methodology that meets changing requirements for wireless designers as they develop new and increasingly more innovative products."

A reference design flow is available through UMC's customer support channels. The live demonstration of this reference design flow for a 2.4GHz, 4GHz and 7GHz LC tank VCO will be presented at CDNLive in HsinChu, Taiwan on Nov. 7.

UMC (NYSE: UMC, TSE: 2303) is a leading global semiconductor foundry that manufactures advanced process ICs for applications spanning every major sector of the semiconductor industry. UMC delivers cutting-edge foundry technologies that enable sophisticated system-on-chip (SoC) designs, including volume production 90nm, industry-leading 65nm, and mixed signal/RFCMOS. UMC's 10 wafer manufacturing facilities include two advanced 300mm fabs; Fab 12A in Taiwan and Singapore-based Fab 12i are both in volume production for a variety of customer products. The company employs approximately 12,000 people worldwide and has offices in Taiwan, Japan, Singapore, Europe, and the United States. UMC can be found on the web at http://www.umc.com.

Cadence enables global electronic-design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. Cadence reported 2005 revenues of approximately $1.3 billion, and has approximately 5,200 employees. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.

Note From UMC Concerning Forward-Looking Statements
Some of the statements in the foregoing announcement are forward looking within the meaning of the U.S. Federal Securities laws, including statements about future outsourcing, wafer capacity, technologies, business relationships and market conditions. Investors are cautioned that actual events and results could differ materially from these statements as a result of a variety of factors, including conditions in the overall semiconductor market and economy; acceptance and demand for products from UMC; and technological and development risks.

Cadence and Virtuoso, are registered trademarks, and the Cadence logo is a trademark, of Cadence Design Systems, Inc. All other trademarks are the property of their respective owners.