Cadence and UMC Address Increasing Complexity of Mixed-Signal Design with Virtuoso Custom Design Platform -Based Silicon-Proven Reference Flow and 0.18-micron Mixed-Mode Process Design Kit

HSINCHU, Taiwan, and SAN JOSE, Calif.-April 19, 2004 - UMC (NYSE:UMC) and Cadence Design Systems, Inc. (NYSE:CDN) today announced that the two companies have delivered a jointly developed analog reference flow that specifically addresses the increasing complexity of mixed-signal designs. The Cadence Virtuoso custom design platform-based reference flow has been silicon-validated using UMC's 0.18-micron mixed-mode CMOS process.

Cadence and UMC have developed a process design kit (PDK) that targets the UMC 0.18-micron mixed-mode CMOS process technology. The two companies continue to develop PDKs targeted at the various UMC process technologies and are working to establish an optimized silicon design chain to reduce design risk while enabling the shortest path from design to volume production for mutual customers. This best-of-breed 0.18-micron, mixed-mode (MM) PDK is intended to simplify the increasing complexity found in mixed-signal designs.

Ken Liou, director of UMC's Design Support division, said, "The analog reference flow and this newest 0.18-micron MM PDK clearly benefit Cadence and UMC's mutual customers, providing shortened design cycle times and increased assurance that the design will be done right the first time. We are happy to work with Cadence and its Virtuoso custom design platform silicon-accurate flows that addresses complex mixed-signal design challenges."

The proliferation of consumer electronics, including wireless technology, has driven the rise in mixed-signal designs. It is estimated that the total mixed-signal content of a system-on-a-chip (SoC) will rise to more than 70 percent by 2005. With this increasing complexity, collaboration is critical for producing silicon-validated reference flows and PDKs that will ease the design challenges. The combination of jointly developed PDKs, proven analog/mixed-signal solutions from Cadence, and UMC's advanced process technologies enables mixed-signal chip designers to integrate more functionality onto a single chip.

"As the market potential for mixed-signal designs increases, it's critical to develop PDKs and establish proven reference flows to reduce the risk of costly respins that can often result in missing the market window," said Charlie Huang, corporate vice president of business development at Cadence. "The combination of UMC's process technology and our leading Virtuoso platform's analog and mixed-signal design solutions ensures that our customers have a proven path to silicon."

The reference flow utilizes the Cadence Virtuoso platform and verification technologies to offer a complete and comprehensive solution for analog and mixed-signal designs. The Virtuoso platform is the world's first comprehensive platform for fast, silicon-accurate custom, analog, and mixed-signal design. Specifically, the UMC analog reference flow includes the following Cadence technologies: Virtuoso Schematic Editor for schematic capture, Virtuoso XL Layout Editor, Virtuoso Spectre Circuit Simulator, Assura^TM Design Rule Checker (DRC) and Assura Layout vs. Schematic Verifier (LVS) for physical verification, Assura Parasitic Extractor (RCX), and Virtuoso Analog Design Environment for front-to-back analog design automation for full-custom analog IC design.

The 0.18-micron MM PDK is one of several PDKs developed by Cadence and UMC as part of a long-term agreement to help integrate UMC process technology with the Cadence front-to-back design and verification flow for analog and mixed-signal ICs. The result is a design-through-manufacture path that helps customers meet aggressive product schedules for advanced mixed-signal SoCs.

This PDK provides a symbol library and technology file for the design automation flow and DRC-correct parameterized cells to automate device generation. They are validated with the Virtuoso Spectre models in the Cadence analog mixed-signal design solution.

The UMC analog reference flow kit and 0.18-micron MM PDK are currently available at no charge to Cadence/UMC customers, from UMC sales representatives or accessible on-line through MyUMC (my.umc.com). For additional information on the analog reference flow, a data sheet is also available at http://www.umc.com/English/pdf/design_datasheet_0402_03.pdf

UMC (NYSE: UMC, TSE: 2303) is a leading global semiconductor foundry that manufactures advanced process ICs for applications spanning every major sector of the semiconductor industry. UMC delivers cutting-edge foundry technologies that enable sophisticated system-on-chip (SOC) designs, including 90nm copper, 0.13um copper, embedded DRAM, and mixed signal/RFCMOS. UMC is also a leader in 300mm manufacturing; Fab 12A in Taiwan is currently in volume production for a variety of customer products, while Singapore-based UMCi has just entered volume production. UMC employs over 8,500 people worldwide and has offices in Taiwan, Japan, Singapore, Europe, and the United States. UMC can be found on the web at http://www.umc.com.

Cadence is the largest supplier of electronic design technologies, methodology services, and design services. Cadence solutions are used to accelerate and manage the design of semiconductors, computer systems, networking and telecommunications equipment, consumer electronics, and a variety of other electronics-based products. With approximately 4,800 employees and 2003 revenues of approximately $1.1 billion, Cadence has sales offices, design centers, and research facilities around the world. The company is headquartered in San Jose, Calif., and traded on the New York Stock Exchange under the symbol CDN. More information about the company, its products and services is available at www.cadence.com.

Cadence, the Cadence logo, Spectre, Virtuoso and Diva are registered trademarks of Cadence Design Systems, Inc. Cadence Assura is a trademark of Cadence Design Systems, Inc. All trademarks are the property of their respective owners.