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UMC’s 2.5D IC solutions integrate multiple dies side by side using a silicon interposer or silicon bridge structure, significantly shortening signal paths and increasing computing speed. They enable high-speed, high-density die-to-die interconnects to enhance data-transfer bandwidth.

This technology is used in AI computing to enable high-speed interconnects between dies through a silicon interposer or multiple silicon bridge structures. For example, a processor and memory can be co-packaged to increase memory access bandwidth, or multiple identical dies can be connected to work together, enabling die-to-die interconnectivity.

To meet the stable power delivery and power integrity requirements of advanced chips, UMC’s Discrete Deep Trench Capacitor (Discrete DTC) technology provides a compact, high-performance decoupling solution.

Compared with traditional ceramic surface-mount capacitors, UMC’s Discrete DTC maintains more stable capacitance across varying temperature and voltage conditions. It also offers excellent equivalent series inductance (ESL) characteristics while requiring less space. These advantages allow Discrete DTCs to be flexibly placed on the substrate’s land side or in silicon, supporting DC decoupling in the power distribution network (PDN) and improving overall power integrity.

Discrete DTCs are particularly well suited to designs with high transient power demands, including AI/HPC accelerators, CPUs, GPUs, and chiplet-based packages.

UMC’s 3D IC solution uses wafer-to-wafer (W2W) hybrid bonding to connect stacked wafers at high density. It supports both heterogeneous integration, such as stacking logic and memory wafers, and homogeneous integration, such as stacking memory wafers. This helps fit more functionality into a limited package footprint.

The solution is well suited for AI accelerators, high-performance computing, stacked memory, and RF devices that need fast, efficient access to local data.