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UMC began shipping 14nm customer wafers in early 2017 and has achieved industry-competitive yields for this advanced FinFET process, which is being utilized for leading-edge high performance electronic applications. UMC’s14nm production takes place at the company’s Fab 12A in Tainan, Taiwan and we plan to steadily ramp 14nm manufacturing capacity according to customer demand.

UMC's self-developed 14nm FinFET technology features advancements such as Fin module, High-k/Metal Gate stack, low-k spacer, strain engineering, and MoL (middle of line) as well as BEOL (back end of line) modules. This process technology is ideal for applications that require high performance and low power consumption within the same design.

UMC’s 22nm process , an optimized platform from based on UMC's 28nm technology for performance enhancement, is currently in volume production. The 22nm superset technology includes both ultra-low power (ULP) and ultra-low leakage (ULL) options on the same platform. It has the same mask count and compatible design rules with the company’s 28nm technology, offering better performance with no added complexity. Chip designers can confidently use UMC’s 22nm design guidelines to gain area benefits and additional performance.

The 22nm process platform has fundamental IP support for various semiconductor applications in the market, including consumer electronics such as set-top boxes, digital TVs, monitors, and power or leakage-sensitive IoT chips (with Bluetooth or Wi-Fi) that are more Ideal for wearables requiring extended battery life.

Our 28nm process technology uses new stress techniques (SMT, t-CESL, c-CESL) and embedded SiGe to enhance electron mobility performance, and is ideal for applications that require high performance and low power consumption. We have years of experience in high volume production for numerous customer products on both UMC's 28 HLP SiON and 28 HPC / HPC+ High-K-Metal Gate processes and have ample capacity to meet the high customer demand for this popular mainstream process technology.

UMC is a leading semiconductor foundry provider of 40nm technology, having delivered customer products on this advanced process node since 2008. UMC's 40nm Low Power (40LP) platform can meet various design application needs, starting with our flexible 40nm technology design platform. Customers are then able to choose the process device options that are optimized for their specific application, such as high performance and low power transistors.

UMC 40nm Ultra Low Power (40uLP) is evolved from the 40nm low power technology (40LP) to generate a lower operation voltage platform in order to meet lower power consumption and lower leakage application requirement. UMC’s ultra-low power (40uLP) process consists of interface IP, IP subsystems, logic libraries, embedded memories and analog IP, which optimized two clusters of process/voltage/temperatures (PVTs), giving designers the ability to increase performance over conventional total corners.

Many chips required for modern electronics such as computers, mobile communication power management chips, RF front-end chips, medium and large size LCD screen driver chips, microcontrollers, audio chips, automotive electronics, etc., are produced on mature 6” and 8" foundry technologies. This process technology ranges from 5 to 0.11 um, providing customers with a variety of application options, and can provide customized processes to meet the rapidly evolving market and serve the increasing demand for semiconductor chips.

In June of 2005, UMC became the first foundry in the world to deliver 65nm customer products. UMC's 65nm technology supports high performance (65SP) and low power (65LL/65LP) requirements for a broad range of mainstream applications.

UMC's 65-nanometer SoC solution begins with a flexible technology design platform. Customers are able to choose the process device options that are optimized for their specific application, such as Standard Performance (SP), Low Leakage (LL) or Low Power (LP) transistors. The high performance characteristics of UMC's 65nm SP process enable designers to utilize the technology to power a broad range of applications from consumer products to graphics ICs. Technology options can also be implemented including mixed signal/RFCMOS to further customize the process.

UMC's 55nm standard performance process (55SP) is a 90% shrink from the 65nm node (65SP), providing customers with smaller die size while maintaining the same performance with similar or lower power. In addition to this standard performance platform (55SP), we also provide a Low Power platform (55LP) and an Ultra Low Power platform (55uLP) options that are compatible with the industry standard processes. All of these platforms are ample capacity and high yield maturity.

UMC has been shipping customer products based on its 90-nanometer (0.09-µm) logic process since March of 2003.

UMC offers low-k or FSG for its 90nm manufacturing, giving customers the flexibility to choose the dielectric material best suited for their particular product application. Companies demanding performance, density, and power efficiency will benefit from UMC's 90nm technology.