Given the deep sub-micron design challenges that circuit designers are facing, UMC Digital Design Reference Flows provide customers. The guideline to use standard cell library and sign-off criteria provided by different library vendors, technology files usage during implementation. The UMC Digital Design Reference Flows incorporate 3rd-party EDA vendor's baseline design flows to address issues such as timing closure, signal integrity, and power consumption built upon silicon validated process libraries. The UMC Digital Design Reference Flows cover from RTL Synthesis, Design-for-Test, Place-and-Route, RC Extraction, Static Timing Analysis to Physical Verification; that include Cadence, Mentor and Synopsys EDA tools.
The UMC Digital Design Reference Flows minimize or eliminate any library, technology, tool and flow issues prior to customers' using the libraries and technology file during implementation. In brief, it significantly shortens :
Time to Tape out
Time to Market
Time to Volume