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聯華電子今日 (10日) 與晶片設計解決方案供應商美商捷碼科技 (Magma® Design Automation Inc.) 共同宣佈,採用聯華電子 65 奈米設計單元資料庫,已經完成驗證統一功率格式 (Unified Power Format, UPF) 相容的低功率 RTL-to-GDSII 參考設計流程。此流程採用 Talus® 晶片實作系統,包含 Talus Power Pro 與整合的捷碼科技設計環境為基礎,運用了先進的低功率設計法則,在獲得設計品質最佳化與提高設計成功機率時,同時也能將功率消耗減到最低。 驗證過程包括了採用統一功率格式相容規格實作一個複雜的功耗設計,接著多重電源區塊可以自動被產生,而其中包含了電壓準位移轉單元,隔離單元與狀態保存暫存器的置入。此設計流程採用聯華電子 65 奈米製程低功率設計單元資料庫,展示統一功率格式相容成功用在降低功率的設計上。 “這個由聯華電子與捷碼科技合作推出之統一功率格式相容的低功率參考設計流程,可為晶片設計公司帶來十分顯著的優勢,”聯華電子全球矽智財支援副總經理徐明志表示,“捷碼科技的軟體支援統一功率格式,在採用包括自動多重電壓設計,極低功耗時脈樹合成與實體實作的尖端技術時,亦能達到動態與漏電功耗的需求。聯華電子的製程技術提供了低漏電電晶體以協助進一步降低晶片的功率消耗。” “許多捷碼科技的客戶係從事無線與可攜式消費性產品晶片的研發,這些設計需要快速的週轉時間以及低功耗。”捷碼科技設計實作事業群總經理 Kam Kittrell 表示。“統一功率格式使得晶片設計公司得以將功耗議題完整的在設計過程中被考慮,節省時間並降低功耗。藉由攜手提供統一功率格式相容的流程,雙方公司可為晶片設計公司帶來自 RTL 設計到低功耗晶片之更簡化的流程。” |
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Talus: An Advanced Low-Power Design Flow |
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The Magma-UMC UPF Low-power Reference Flow is based on the Talus implementation system. This system provides a fully integrated RTL-to-GDSII flow for high-performance, high-complexity, low-power nanometer designs. Talus Design and Talus Vortex are key components of the system. Talus Design is a full-chip synthesis environment that enables rapid development of RTL and chip-level constraints throughout the design process, and automates data-path synthesis and floorplan generation for prototyping. Talus Vortex is a physical design environment that delivers improved timing and signal integrity, smaller area, lower power, better manufacturability, faster turnaround time and higher capacity than conventional point-tool flows. Talus Power Pro works in conjunction with Talus Design and Talus Vortex to enable optimal power management throughout the flow. It features power-aware synthesis, physical optimization, clock tree synthesis and routing, allowing designers to minimize power and ensure uniform power distribution. Talus Power Pro reads in the power constraints from the UPF file at the beginning of the RTL-to-GDSII flow. Power constraints such as clock gating, retention-flop synthesis and multi-Vdd domain definitions can be defined for dynamic power reduction. Special cells such as level shifters and isolation cells can be inferred during the synthesis stage to support multi-Vdd flows. For domains that are powered down, switches can be inferred at the RTL stage to facilitate simulation. State tables can be used to define the relationship between the different domains that have been created. Talus Power Pro can also write out UPF files at any point in the design flow for easy interoperability with third-party tools. |
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About Magma |
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Magma's software for designing integrated circuits (ICs) is used to create complex, high-performance chips required in cellular telephones, electronic games, WiFi, MP3 players, DVD/digital video, networking, automotive electronics and other electronic applications. Magma's EDA software for IC implementation, analysis, physical verification, circuit simulation and characterization is recognized as embodying the best in semiconductor technology, enabling the world's top chip companies to "Design Ahead of the Curve"TM while reducing design time and costs. Magma is headquartered in San Jose, Calif., with offices around the world. Magma's stock trades on Nasdaq under the ticker symbol LAVA. Visit Magma Design Automation on the Web at www.magma-da.com. Magma and Talus are registered trademarks and "Design Ahead of the Curve" is a trademark of Magma Design Automation Inc. All other product and company names are trademarks or registered trademarks of their respective companies. Forward-looking Statements: |
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